Furthermore, we explore the use of the Intel Optane DC Persistent Memory Module (PMEM) to make FEDB more cost-effective. Our experimental results show that FEDB can be one to two orders of magnitude faster than the state-of-the-art in-memory databases on real-time feature extraction.
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We therefore propose FEDB (Feature Engineering Database), a distributed in-memory database system designed to efficiently support on-line feature extraction. This is unacceptable for OLDA applications with strict realtime constraints. However, we found that existing in-memory databases cost hundreds or even thousands of milliseconds. In this work, we started by studying how existing in-memory databases can be leveraged to efficiently support such real-time feature extractions. Feature extraction is usually the most time-consuming operation in many OLDA data pipelines.
WALKING PAPERS RAR WINDOWS
On-line inference puts real-time features extracted from multiple time windows through a pre-trained model to evaluate new data to support decision making. OLDA has been widely used in many applications such as real-time fraud detection, personalized recommendation, etc. On-line decision augmentation (OLDA) has been considered as a promising paradigm for real-time decision making powered by Artificial Intelligence (AI). Weng-Fai Wong (National University of Singapore), On-line Decision Augmentation Using Persistent Memory Cheng Chen (4Paradigm Inc.),īingsheng He (National University of Singapore), Optimizing In-memory Database Engine For AI-powered As a result, for the synthetic and real-world graphs, the execution times of the graph algorithms are 88-141% of those when all the data are placed in DRAM. In our evaluation, the large graph data is placed on microsecond-latency flash memories within prototype boards, and it is accessed by the proposed method. We apply the proposed method to graph algorithms such as BFS (Breadth First Search), which involves many small-sized random read accesses.
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These reduce the CPU overhead per request to less than 10 nsec, enabling read access with DRAM-like overhead, while the access latency longer than DRAM can be hidden by the context switches. 2) utilizing many contexts with lightweight context switches by stackless coroutines. To tackle the problem, we propose a new access method combining two approaches: 1) optimizing issuance and completion of the IO requests to reduce the CPU overhead. However, when they are used in large numbers to achieve high IOPS (Input/Output operations Per Second), the CPU processing involved in IO requests is an overhead. For the read-intensive case we focus on in this paper, low latency flash memory with microsecond read latency is a promising solution. Graph applications Tomoya Suzuki (Kioxia Corporation),įor applications in which small-sized random accesses frequently occur for datasets that exceed DRAM capacity, placing the datasets on SSD can result in poor application performance. Microsecond-latency flash memory for small-sized random read accesses: a new access method and its Persistent Memory I Chaired by Peter Boncz